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TMS320C5515
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
Table 5-48. Universal Serial Bus (USB) Registers (1) (continued)
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CPU WORD
ADDRESS
8401h
8402h
8405h
8406h
8409h
840Ah
840Dh
840Eh
8411h
8412h
8415h
8416h
8419h
841Ah
841Dh
841Eh
ACRONYM
FADDR_POWER
INTRTX
INTRRX
INTRTXE
INTRRXE
INTRUSB_INTRUSBE
FRAME
INDEX_TESTMODE
TXMAXP_INDX
PERI_CSR0_INDX
PERI_TXCSR_INDX
RXMAXP_INDX
PERI_RXCSR_INDX
COUNT0_INDX
RXCOUNT_INDX
-
-
CONFIGDATA_INDC
REGISTER DESCRIPTION
Common USB Registers
Function Address Register, Power Management Register
Interrupt Register for Endpoint 0 plus Transmit Endpoints 1 to 4
Interrupt Register for Receive Endpoints 1 to 4
Interrupt enable register for INTRTX
Interrupt Enable Register for INTRRX
Interrupt Register for Common USB Interrupts, Interrupt Enable Register
Frame Number Register
Index Register for Selecting the Endpoint Status and Control Registers, Register to
Enable the USB 2.0 Test Modes
USB Indexed Registers
Maximum Packet Size for Peripheral/Host Transmit Endpoint. (Index register set to
select Endpoints 1-4)
Control Status Register for Endpoint 0 in Peripheral Mode. (Index register set to
select Endpoint 0)
Control Status Register for Peripheral Transmit Endpoint. (Index register set to select
Endpoints 1-4)
Maximum Packet Size for Peripheral/Host Receive Endpoint. (Index register set to
select Endpoints 1-4)
Control Status Register for Peripheral Receive Endpoint. (Index register set to select
Endpoints 1-4)
Number of Received Bytes in Endpoint 0 FIFO. (Index register set to select Endpoint
0)
Number of Bytes in Host Receive Endpoint FIFO. (Index register set to select
Endpoints 1- 4)
Reserved
Reserved
Returns details of core configuration. (index register set to select Endpoint 0)
(Upper byte of 841Eh)
USB FIFO Registers
8421h
8422h
8425h
8426h
8429h
842Ah
842Dh
842Eh
8431h
8432h
8461h
8462h
8465h
8466h
846Dh
FIFO0R1
FIFO0R2
FIFO1R1
FIFO1R2
FIFO2R1
FIFO2R2
FIFO3R1
FIFO3R2
FIFO4R1
FIFO4R2
-
TXFIFOSZ_RXFIFOSZ
TXFIFOADDR
RXFIFOADDR
-
Transmit and Receive FIFO Register 1 for Endpoint 0
Transmit and Receive FIFO Register 2 for Endpoint 0
Transmit and Receive FIFO Register 1 for Endpoint 1
Transmit and Receive FIFO Register 2 for Endpoint 1
Transmit and Receive FIFO Register 1 for Endpoint 2
Transmit and Receive FIFO Register 2 for Endpoint 2
Transmit and Receive FIFO Register 1 for Endpoint 3
Transmit and Receive FIFO Register 2 for Endpoint 3
Transmit and Receive FIFO Register 1 for Endpoint 4
Transmit and Receive FIFO Register 2 for Endpoint 4
Dynamic FIFO Control Registers
Reserved
Transmit Endpoint FIFO Size, Receive Endpoint FIFO Size (Index register set to
select Endpoints 1-4)
Transmit Endpoint FIFO Address (Index register set to select Endpoints 1-4)
Receive Endpoint FIFO Address (Index register set to select Endpoints 1-4)
Reserved
140
Peripheral Information and Electrical Specifications
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